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Intel price list: Xeon with 2 MB L2 cache, global price reduction ? ahead

Earlier this week, Intel added new products to its server Xeon lineup designed for single / dual-processor configurations. Compared to previous models of E0 stepping (core code name – Nocona), the new Xeon processors based on N0 stepping (code name – Irwindale, signature CPUID = 0F43h) have not so many differences: in fact, only the increased L2 cache is reported from 1 Mb up to 2 Mb. Accordingly, all the innovations that took place in the early stepping (EM64T, XD-Bit, Thermal Monitor 2, C1E, DBS, SSE3, Hyper-Threading …) have been preserved.

An increase in the number of transistors in the Irwindale core (+ 1 MB of L2 cache) had a positive effect on performance: according to Intel experts, in some applications it increased up to 18%, compared to the results of earlier models based on the Nocona core. However, this had a negative effect on power consumption: with the same 90 nm process technology, the 800 MHz TDP bus QP of the new Xeon N0 stepping was increased from 103 W (E0) to 110 W. Processors, as usual, have 604-pin PPGA packaging, the prices for the four debuted models are set as follows:

CPU
Price (from 1000 pcs.)
Xeon 3.6 GHz
851 USD.
Xeon 3.4 GHz
690 USD.
Xeon 3.2 GHz
455 USD.
Xeon 3.0 GHz
US $ 316.

    * sSpec of models is available here

In Japan, working dual-processor systems based on the new 3.4 GHz Xeon are already being demonstrated, and for these purposes the X6DAE-G2 motherboard from Supermicro was used without problems (E7525 chipset, it is stated that Irwindale is also capable of interoperability with the E7320 and E7520).

“Japanese” Sandra from SiSoftware is still mistaken when defining Irwindale characteristics, for example, in the name of the kernel, but the 2 MB L2 cache “sees” clearly:

IBM, NEC, HP, as well as 14 other smaller vendors, including Hitachi and Fujitsu, expressed their desire to supply ready-made systems based on the new Xeon. E0 stepping processors (in Japan) will appear on sale in early March.

Among other things, Intel announced the Intel IOP333 I / O chip based on the Intel XScale architecture, which allows building data storage systems based on it in the form of RAID level 6. Also mentioned were the future Xeon MPs (Potomac core with 8 MB L3 cache and entry-level Cranford core with 2 MB L2 cache), which the corporation is going to present within the next three months.

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